1. Technical Field
The inventive concept relates to a voltage boosting circuit, and more particularly, to a high voltage generating circuit for a resistive memory apparatus.
2. Related Art
High voltage generating circuits are circuits configured to boost an input voltage to a desired level and output the boosted voltage.
FIG. 1 is an illustrative view of a related high voltage generating circuit.
First, when a first switch S1 and a third switch S3 are closed, a power voltage VDD having an input voltage level is charged in a capacitor CAP. Subsequently, when the first switches S1 and the third switch S3 are opened and a second switch S2 is closed, a value of VDD*C is charged and held in the capacitor CAP. Assuming that there is no an output load, an output voltage twice the input voltage VDD can be obtained.
In semiconductor integrated circuits, the high voltage generating circuit is generally formed using a MOS transistor and a MOS capacitor. Since the MOS devices are used in the high voltage generating circuit, a silicon substrate has no choice but to be used in fabricating the high voltage generating circuit. A gate oxide layer constituting the MOS transistor and the MOS capacitor has a low dielectric constant. Therefore, an occupied area of the general high voltage generating circuit is inevitably increased in proportional to the output level.
Resistive memory apparatuses, particularly, phase-change random access memory (PCRAM) apparatuses require a large amount of current to transit a crystalline state of a phase-change material and thus the voltage level required to operate memory cells in a chip has to be increased. The high voltage generating circuit required to operate PCRAM cells is formed in a peripheral circuit area and will be described below with reference to FIG. 2.
FIG. 2 is an illustrative diagram of a related resistive memory apparatus, for example, a PCRAM device.
A semiconductor substrate 101 includes a cell area C and a peripheral circuit area P defined by a device isolation layer and memory cells 107 are formed in the cell area C. More specifically, a plurality of unit memory cells 107 are formed on an active region 105 of the cell area C and each unit memory cell 107 is electrically connected to a bit line 109 through a plug. The active region 105 is electrically connected to a word line 115 through a word line contact 111 and a dummy pattern 113. The reference numeral 103 designates a well region and the reference numeral 117 designates a global bit line.
The peripheral circuit area P may include a capacitor region Cap for high voltage generation, a transistor region Tr, and a logic circuit region Tr-L.
As illustrated in FIG. 2, a capacitor and transistor formed in a high voltage generation regions Cap and Tr are a silicon substrate-based MOS device. However, a gate oxide layer of a MOS transistor has a very low dielectric constant and thus, a size of the MOS capacitor is inevitably increased with increase in an output voltage level.
In a recently developed PCRAM, an, area share of a reservoir capacitor in a chip is approximately 17.2% and an area share of the reservoir capacitor to the peripheral circuit area is approximately 34.7%. An area share of a high voltage generating circuit in the chip is approximately 8.4% and an area share of the high voltage generating circuit to the peripheral circuit area is approximately 16.9%. Therefore, an area of the peripheral circuit area, occupied by the reservoir capacitor and the high voltage generating circuit reaches 51.6%
The semiconductor devices have been highly integrated and miniaturized increasingly and thus it is necessary to reduce in an occupied area or a size of the peripheral circuit area.